Low voltage differential signaling (LVDS) is a high-speed digital interface that has become the primary technology for applications that require low power consumption and high noise immunity for high data rates. LVDS is standardized under ANSI/TIA/EAI-644, which provides guidelines that define the electrical characteristics for the LVDS driver output and the receiver input of the LVDS interface.
While LVDS implementations provide significant advantages in applications requiring high data transfer rates, LVDS circuits are not immune to process and environmental conditions. The conditions affecting the LVDS circuits may include process variations (P), power supply voltage variations (V) and operating temperature variations (T), commonly referred to collectively as PVT variations. The steering current provided by the LVDS driver to a load changes as a result of these PVT variations, which directly affects the amplitude of the differential output voltage of the LVDS driver.
Additionally, LVDS circuits are commonly designed to drive a steering current for an individual load. As such, when multiple loads are coupled to a common output of an LVDS driver, the steering current must drive multiple loads, resulting in a undesirable reduction of the amplitude of the differential output voltage of the LVDS driver because the current is divided by the number of loads that are connected to the output.
Accordingly, what is needed in the art is an improved system and method for regulating the amplitude of the output voltage of a low voltage differential signaling (LVDS) driver under varying PVT conditions and under multiple load situations.